RISC architecture

RISC stands for reduced instruction set computer. It is a type of microprocessor architecture which utilizes a small, highly optimized instructions set rather than a more specialized set of instructions normally found in other types of architecture. Hence each instruction that a computer must perform, requires additional transistors and circuitry, a larger set of computer instructions makes the microprocessor more complicated and slower in operation. The RISC processor has hardwired control unit. Below figure shows the RISC architecture with hardwired control unit with split cache.

RISC architecture

RISC architecture

The RISC processor can operate at a higher speed i.e. perform more millions of instructions per second. Register to register operations support only load and store operations to access memory and rest of the operations on a register to register basis. RISC processor has simple and few addressing modes. RISC processor has large number of registers which are needed to support register to register operations minimize the procedure call and return overhead. The RISC processor has fixed-length instructions facilitates efficient instruction execution and easy to pipeline. It easier to develop code with a smaller instruction set for operating system and application. RISC processors have a clock per instruction (CPI) of one cycle due to the optimization of each instruction on the CPU.

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